The semiconductor integrated circuit (IC) industry has experienced rapid growth. During this growth, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, stricter demands have been placed on the lithography process used in such process nodes. Techniques such as extreme ultraviolet (EUV) lithography have been utilized to support critical dimension (CD) requirements of smaller IC devices. Such lithography methods utilize masks which frequently include various defects that introduce fabrication defects in the smaller IC devices. Certain compensation methods, such as repairing mask defects, may be utilized. These compensation methods, however, may significantly increase mask fabrication time and cost. Accordingly, although existing lithography methods have been generally adequate, they have not been satisfactory in all respects.